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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with nec electronics sales representative for availability and additional information. mos integrated circuit pd44321182, 44321362 32m-bit zerosb tm sram pipelined operation document no. m16024ej5v0ds00 (5th edition) date published april 2005 ns cp(k) printed in japan data sheet the mark shows major revised points. 2002, 2005 description the pd44321182 is a 2,097,152-word by 18-bit and the pd44321362 is a 1,048,576-word by 36-bit zerosb static ram fabricated with advanced cmos technolo gy using full cmos six-tr ansistor memory cell. the pd44321182 and pd44321362 are optimized to eliminate dead cycl es for read to write, or write to read transitions. these zerosb static rams integrate unique synchronous peripheral circuitry, 2-bit burst counter and output buffer as well as sram core. all input registers ar e controlled by a positive edge of the single clock input (clk). the pd44321182 and pd44321362 are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit c onfiguration, such as buffer memory. zz has to be set low at the normal oper ation. when zz is set high, the sram enters power down state (?sleep?). in the ?sleep? state, the sram inte rnal state is preserved. when zz is set low again, the sram resumes normal operation. the pd44321182 and pd44321362 are packaged in 100-pin plastic lqfp with a 1.4 mm package thickness for high density and low capacitive loading. features ? low voltage core supply : v dd = 3.3 0.165 v / 2.5 0.125 v ? synchronous operation ? 100 percent bus utilization ? internally self-timed write control ? burst read / write : interleaved burst and linear burst sequence ? fully registered inputs and outputs for pipelined operation ? all registers triggered off positive clock edge ? 3.3v or 2.5v lvttl compat ible : all inputs and outputs ? fast clock access time : 3.2 ns (200 mhz) ? asynchronous output enable : /g ? burst sequence selectable : mode ? sleep mode : zz (zz = open or low : normal operation) ? separate byte write enable : /bw1 to /bw4 ( pd44321362) /bw1 and /bw2 ( pd44321182) ? three chip enables for easy depth expansion ? common i/o using th ree state outputs
2 data sheet m16024ej5v0ds pd44321182, 44321362 ordering information part number access time ns clock frequency mhz core supply voltage v i/o interface package pd44321182gf-a50 3.2 200 3.3 0.165 3.3 v or 2.5 v lvttl 100-pin plastic lqfp 2.5 0.125 2.5 v lvttl (14 x 20) pd44321362gf-a50 3.2 200 3.3 0.165 3.3 v or 2.5 v lvttl 2.5 0.125 2.5 v lvttl
3 data sheet m16024ej5v0ds pd44321182, 44321362 pin configurations / indicates active low signal. 100-pin plastic lqfp (14 20) [ pd44321182gf] marking side nc nc nc v dd q v ss q nc nc i/o9 i/o10 v ss q v dd q i/o11 i/o12 v dd v dd v dd v ss i/o13 i/o14 v dd q v ss q i/o15 i/o16 i/op2 nc v ss q v dd q nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 a20 nc nc v dd q v ss q nc i/op1 i/o8 i/o7 v ss q v dd q i/o6 i/o5 v ss v dd v dd zz i/o4 i/o3 v dd q v ss q i/o2 i/o1 nc nc v ss q v dd q nc nc nc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 a6 a7 /ce ce2 nc nc /bw2 /bw1 /ce2 v dd v ss clk /we /cke /g adv a18 a17 a8 a9 mode a5 a4 a3 a2 a1 a0 nc nc v ss v dd nc a19 a10 a11 a12 a13 a14 a15 a16 remark refer to package drawings for the 1-pin index mark.
4 data sheet m16024ej5v0ds pd44321182, 44321362 pin identifications [ pd44321182gf] symbol pin no. description a0 to a20 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, synchronous address input 45, 46, 47, 48, 49, 50, 83, 84, 43, 80 i/o1 to i/o16 58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12, 13, synchronous data in, 18, 19, 22, 23 synchronous / asynchronous data out i/op1, i/op2 74, 24 synchronous data in (parity), synchronous / asynchronous data out (parity) adv 85 synchronous address load / advance input /ce, ce2, /ce2 98, 97, 92 synchronous chip enable input /we 88 synchronous write enable input /bw1, /bw2 93, 94 synchronous byte write enable input /g 86 asynchronous output enable input clk 89 clock input /cke 87 synchronous clock enable input mode 31 asynchronous burst sequence select input have to tied to v dd or v ss during normal operation zz 64 asynchronous power down state input v dd 14, 15, 16, 41, 65, 66, 91 power supply v ss 17, 40, 67, 90 ground v dd q 4, 11, 20, 27, 54, 61, 70, 77 output buffer power supply v ss q 5, 10, 21, 26, 55, 60, 71, 76 output buffer ground nc 1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42, 51, no connection 52, 53, 56, 57, 75, 78, 79, 95, 96
5 data sheet m16024ej5v0ds pd44321182, 44321362 100-pin plastic lqfp (14 20) [ pd44321362gf] marking side i/op3 i/o17 i/o18 v dd q v ss q i/o19 i/o20 i/o21 i/o22 v ss q v dd q i/o23 i/o24 v dd v dd v dd v ss i/o25 i/o26 v dd q v ss q i/o27 i/o28 i/o29 i/o30 v ss q v dd q i/o31 i/o32 i/op4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 i/op2 i/o16 i/o15 v dd q v ss q i/o14 i/o13 i/o12 i/o11 v ss q v dd q i/o10 i/o9 v ss v dd v dd zz i/o8 i/o7 v dd q v ss q i/o6 i/o5 i/o4 i/o3 v ss q v dd q i/o2 i/o1 i/op1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 a6 a7 /ce ce2 /bw4 /bw3 /bw2 /bw1 /ce2 v dd v ss clk /we /cke /g adv a18 a17 a8 a9 mode a5 a4 a3 a2 a1 a0 nc nc v ss v dd nc a19 a10 a11 a12 a13 a14 a15 a16 remark refer to package drawings for the 1-pin index mark.
6 data sheet m16024ej5v0ds pd44321182, 44321362 pin identifications [ pd44321362gf] symbol pin no. description a0 to a19 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, synchronous address input 45, 46, 47, 48, 49, 50, 83, 84, 43 i/o1 to i/o32 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, synchronous data in, 73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, synchronous / asynchronous data out 18, 19, 22, 23, 24, 25, 28, 29 i/op1 to i/op4 51, 80, 1, 30 synchronous data in (parity), synchronous / asynchronous data out (parity) adv 85 synchronous address load / advance input /ce, ce2, /ce2 98, 97, 92 synchronous chip enable input /we 88 synchronous write enable input /bw1 to /bw4 93, 94, 95, 96 synchronous byte write enable input /g 86 asynchronous output enable input clk 89 clock input /cke 87 synchronous clock enable input mode 31 asynchronous burst sequence select input have to tied to v dd or v ss during normal operation zz 64 asynchronous power down state input v dd 14, 15, 16, 41, 65, 66, 91 power supply v ss 17, 40, 67, 90 ground v dd q 4, 11, 20, 27, 54, 61, 70, 77 output buffer power supply v ss q 5, 10, 21, 26, 55, 60, 71, 76 output buffer ground nc 38, 39, 42 no connection
7 data sheet m16024ej5v0ds pd44321182, 44321362 block diagrams [ pd44321182] a0 to a20 mode clk /cke adv /bw1 /bw2 /we /g /ce ce2 /ce2 address register 0 burst logic write address register 0 write registry and data coherency control logic write drivers data steering adv k a1 a0 a1? a0? sense amplifiers read logic input register 0 e output buffers e i/o1 to i/o16 i/op1, i/op2 21 19 21 21 21 18 18 18 18 write address register 1 output registers e input register 1 e 18 zz power down control k memory cell array 2,048 x 18 columns (37,748,736 bits) 1,024 rows burst sequence [ pd44321182] interleaved burst sequence table (mode = v dd ) external address a20 to a2, a1, a0 1st burst address a20 to a2, a1, /a0 2nd burst address a20 to a2, /a1, a0 3rd burst address a20 to a2, /a1, /a0 linear burst sequence table (mode = v ss ) external address a20 to a2, 0, 0 a20 to a2, 0, 1 a20 to a2, 1, 0 a20 to a2, 1, 1 1st burst address a20 to a2, 0, 1 a20 to a2, 1, 0 a20 to a2, 1, 1 a20 to a2, 0, 0 2nd burst address a20 to a2, 1, 0 a20 to a2, 1, 1 a20 to a2, 0, 0 a20 to a2, 0, 1 3rd burst address a20 to a2, 1, 1 a20 to a2, 0, 0 a20 to a2, 0, 1 a20 to a2, 1, 0
8 data sheet m16024ej5v0ds pd44321182, 44321362 [ pd44321362] a0 to a19 mode clk /cke adv /bw1 /bw2 /we /g /ce ce2 /ce2 address register 0 burst logic write address register 0 write registry and data coherency control logic write drivers data steering adv k a1 a0 a1? a0? sense amplifiers read logic input register 0 e output buffers e i/o1 to i/o32 i/op1 to i/op4 20 18 20 20 20 36 36 36 36 write address register 1 output registers e input register 1 e 36 /bw3 /bw4 zz power down control k memory cell array 1,024 x 36 columns (37,748,736 bits) 1,024 rows burst sequence [ pd44321362] interleaved burst sequence table (mode = v dd ) external address a19 to a2, a1, a0 1st burst address a19 to a2, a1, /a0 2nd burst address a19 to a2, /a1, a0 3rd burst address a19 to a2, /a1, /a0 linear burst sequence table (mode = v ss ) external address a19 to a2, 0, 0 a19 to a2, 0, 1 a19 to a2, 1, 0 a19 to a2, 1, 1 1st burst address a19 to a2, 0, 1 a19 to a2, 1, 0 a19 to a2, 1, 1 a19 to a2, 0, 0 2nd burst address a19 to a2, 1, 0 a19 to a2, 1, 1 a19 to a2, 0, 0 a19 to a2, 0, 1 3rd burst address a19 to a2, 1, 1 a19 to a2, 0, 0 a19 to a2, 0, 1 a19 to a2, 1, 0
9 data sheet m16024ej5v0ds pd44321182, 44321362 state diagram deselect begin read burst read begin write burst write write read read ds ds write read burst burst write read write read burst write burst ds burst ds ds command operation ds deselect read new read write new write burst burst read, burst write or continue deselect remarks 1. states change on the risi ng edge of the clock. 2. a stall or ignore clock edge cycle is not shown in the above diagram. this is because /cke high only blocks the clock (clk) input and does not change the state of the device.
10 data sheet m16024ej5v0ds pd44321182, 44321362 asynchronous truth table operation /g i/o read cycle l data-out read cycle h high-z write cycle high-z, data-in deselected high-z remark : don?t care synchronous truth table operation /ce ce2 /ce2 adv /we /bws /cke clk i/o address note deselected h l l l h high-z none 1 deselected l l l l h high-z none 1 deselected h l l l h high-z none 1 continue deselected h l l h high-z none 1 read cycle / begin burst l h l l h l l h data-out external read cycle / continue burst h l l h data-out next write cycle / begin burst l h l l l l l l h data-in external write cycle / continue burst h l l l h data-in next write cycle / write abort l h l l l h l l h high-z external write cycle / write abort h h l l h high-z next stall / ignore clock edge h l h ? current 2 notes 1. deselect status is held until new ?begin burst? entry. 2. if an ignore clock edge command occurs during a read o peration, the i/o bus will remain active (low- impedance). if it occurs during a write cycle, the bus will remain high impedance. no write operation will be performed during the ignore clock edge cycle. remarks 1. : don?t care 2. /bws = l means any one or more byte write enables (/bw1, /bw2, /bw3 or /bw4) are low. /bws = h means all byte write enables (/bw1, /bw2, /bw3 or /bw4) are high.
11 data sheet m16024ej5v0ds pd44321182, 44321362 partial truth table for write enables [ pd44321182] operation /we /bw1 /bw2 read cycle h write cycle / byte 1 (i/o [1:8], i/op1) l l h write cycle / byte 2 (i/o [9:16], i/op2) l h l write cycle / all bytes l l l write abort / nop l h h remark : don?t care [ pd44321362] operation /we /bw1 /bw2 /bw3 /bw4 read cycle h write cycle / byte 1 (i/o [1:8], i/op1) l l h h h write cycle / byte 2 (i/o [9:16], i/op2) l h l h h write cycle / byte 3 (i/o [17:24], i/op3) l h h l h write cycle / byte 4 (i/o [25:32], i/op4) l h h h l write cycle / all bytes l l l l l write abort / nop l h h h h remark : don?t care zz (sleep) truth table zz chip status 0.2 v active open active v dd ? 0.2 v sleep
12 data sheet m16024ej5v0ds pd44321182, 44321362 electrical specifications absolute maximum ratings parameter symbol conditions min. typ. max. unit supply voltage v dd ?0.5 +4.0 v output supply voltage v dd q ?0.5 v dd v input voltage v in ?0.5 note v dd + 0.5 v input / output voltage v i/o ?0.5 note v dd q + 0.5 v operating ambient t a 0 70 c temperature storage temperature t stg ?55 +125 c note ?2.0 v (min.) (pulse width : 2 ns) caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this speci fication. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended dc operating conditions (v dd = 3.3 0.165 v) (1/2) parameter symbol conditions min. typ. max. unit supply voltage v dd 3.135 3.3 3.465 v 2.5 v lvttl interface output supply voltage v dd q 2.375 2.5 2.9 v high level input voltage v ih 2.0 v dd q + 0.3 v low level input voltage v il ?0.3 note +0.7 v 3.3 v lvttl interface output supply voltage v dd q 3.135 3.3 3.465 v high level input voltage v ih 2.0 v dd q + 0.3 v low level input voltage v il ?0.3 note +0.8 v note ?0.8 v (min.) (pulse width : 2 ns) recommended dc operating conditions (v dd = 2.5 0.125 v) (2/2) parameter symbol conditions min. typ. max. unit supply voltage v dd 2.375 2.5 2.625 v output supply voltage v dd q 2.375 2.5 2.625 v high level input voltage v ih 1.7 v dd q + 0.3 v low level input voltage v il ?0.3 note +0.7 v note ?0.8 v (min.) (pulse width : 2 ns)
13 data sheet m16024ej5v0ds pd44321182, 44321362 dc characteristics (v dd = 3.3 0.165 v or 2.5 0.125 v) parameter symbol test condition min. typ. max. unit input leakage current i li v in (except zz, mode) = 0 v to v dd ?2 +2 a i/o leakage current i lo v i/o = 0 v to v dd q, outputs are disabled. ?2 +2 a operating supply current i dd device selected, cycle = max. 410 ma v in v il or v in v ih , i i/o = 0 ma standby supply current i sb device deselected, cycle = 0 mhz, 70 ma v in v il or v in v ih , all inputs are static. i sb1 device deselected, cycle = 0 mhz, 60 v in 0.2 v or v in v dd ? 0.2 v, v i/o 0.2 v, all inputs are static. i sb2 device deselected, cycle = max. 130 v in v il or v in v ih power down supply current i sbzz zz v dd ? 0.2 v, v i/o v dd q + 0.2 v 60 ma 2.5 v lvttl interface high level output voltage v oh i oh = ?2.0 ma 1.7 v i oh = ?1.0 ma 2.1 low level output voltage v ol i ol = +2.0 ma 0.7 v i ol = +1.0 ma 0.4 3.3 v lvttl interface high level output voltage v oh i oh = ?4.0 ma 2.4 v low level output voltage v ol i ol = +8.0 ma 0.4 v capacitance (t a = 25 c, f = 1mhz) parameter symbol test condition min. typ. max. unit input capacitance c in v in = 0 v 6.0 pf input / output capacitance c i/o v i/o = 0 v 8.0 pf clock input capacitance c clk v clk = 0 v 6.0 pf remark these parameters are periodically sampled and not 100 % tested.
14 data sheet m16024ej5v0ds pd44321182, 44321362 ac characteristics (v dd = 3.3 0.165 v or 2.5 0.125 v) ac test conditions 2.5 v lvttl interface input waveform (rise / fall time 2.4 ns) test points v ss 2.4 v 1.2 v 1.2 v output waveform test points 1.2 v 1.2 v 3.3 v lvttl interface input waveform (rise / fall time 3.0 ns) test points v ss 3.0 v 1.5 v 1.5 v output waveform test points 1.5 v 1.5 v output load condition c l : 30 pf 5 pf (tkhqx1, tkhqx2, tglqx, tghqz, tkhqz) figure external load at test v t = +1.2 v / +1.5 v i/o (output) 50 ? z o = 50 ? c l remark c l includes capacitances of the probe and jig, and stray capacitances.
15 data sheet m16024ej5v0ds pd44321182, 44321362 read and write cycle parameter symbol -a50 (200 mhz) unit notes standard alias min. max. cycle time tkhkh tcyc 5 ? ns clock access time tkhqv tcd ? 3.2 ns output enable access time tglqv toe ? 3.2 ns clock high to output active tkhqx1 tdc1 1.5 ? ns 1, 2 clock high to output change tkhqx2 tdc2 1.5 ? ns output enable to output active tglqx tolz 0 ? ns 1 output disable to output high-z tghqz tohz 0 3.2 ns 1 clock high to output high-z tkhqz tcz 1.5 3.2 ns 1, 2 clock high pulse width tkhkl tch 1.8 ? ns clock low pulse width tklkh tcl 1.8 ? ns setup times address tavkh tas 1.5 ? ns address advance tadvvkh tadvs clock enable tevkh tces chip enable tcvkh tcss data in tdvkh tds write enable twvkh tws hold times address tkhax tah 0.5 ? ns 3 address advance tkhadvx tadvh (1.0) (?) clock enable tkhex tceh chip enable tkhcx tcsh data in tkhdx tdh write enable tkhwx twh power down entry time tzze tzze ? 10 ns power down recovery time tzzr tzzr ? 10 ns notes 1. transition is measured 200 mv from steady state. 2. to avoid bus contention, t he output buffers are designed such that tkhqz (device turn-off) is faster than tkhqx1 (device turn-on) at a gi ven temperature and voltage. the specs as shown do not imply bus contention because tkhqx1 is a min. parameter that is worse case at totally different conditions (t a min., v dd max.) than tkhqz, which is a max. parameter (worse case at t a max., v dd min.). 3. these values apply when v dd = 3.3 v 0.165 v with a 3.3 v lvttl interface, or when v dd = 2.5 v 0.125 v with a 2.5 v lvttl interface. values in parentheses apply when v dd = 3.3 v 0.165 v with a 2.5 v lvttl interface.
16 data sheet m16024ej5v0ds pd44321182, 44321362 read / write cycle write d (a1) clk /cke /ces adv /we data in data out /g /bws address command 12345678910 d (a1) d (a2) d (a2+1) d (a5) q (a3) q (a4) q (a4+1) q (a6) write d (a2) burst write d (a2+1) read q (a3) read q (a4) burst read q (a4+1) write d (a5) read q (a6) write q (a7) deselect tkhkh tevkh tkhex tcvkh tkhcx tkhkl tklkh tdvkh tkhdx tkhqx1 tkhqv tkhqx2 tghqz tglqx tkhqx2 tglqv tkhqz tadvvkh tkhadvx twvkh tkhwx twvkh tkhwx note 1 note 2 a2 a7 tavkh tkhax a1 a3 a4 a5 a6 high-z high-z high-z high-z high-z notes 1. /ces refers to /ce, ce2 and /ce2. when /ces is low, /ce and /ce2 are low and ce2 is high. when /ces is high, /ce and /ce2 are high and ce2 is low. 2. /bws refers to /bw1, /bw2, /bw3 and /bw4. when /bws is low, any one or more byte write enables (/bw1, /bw2, /bw3 or /bw4) are low.
17 data sheet m16024ej5v0ds pd44321182, 44321362 nop, stall and deselect cycle 12345678910 write d (a1) clk /cke /ces adv /we data in data out /bws address command d (a1) d (a4) q (a2) q (a3) q (a5) read q (a2) stall read q (a3) write d (a4) stall nop read q (a5) deselect continue deselect tkhqx2 tkhqz a2 a1 a3 a4 a5 high-z high-z high-z high-z high-z
18 data sheet m16024ej5v0ds pd44321182, 44321362 power down (zz) cycle 12345678910 clk /cke adv /we /g data out address q (a1) 11 12 q1 (a2) zz tkhkh tkhkl tzze tzzr power down (i sbzz ) state a1 a2 /ces note /bws note tklkh high-z high-z note /we or /ces must be held high at clk rising edge (clock edge no.2 and no.3 in this figure) prior to power down state entry.
19 data sheet m16024ej5v0ds pd44321182, 44321362 package drawing 100-pin plastic lqfp (14x20) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 22.0 s100gf-65-8et-1 s 1.7 max. h 0.32 + ? + ? + ?
20 data sheet m16024ej5v0ds pd44321182, 44321362 recommended soldering condition please consult with our sales offices for soldering conditions of the pd44321182 and pd44321362. types of surface mount devices pd44321182gf : 100-pin plastic lqfp (14 x 20) pd44321362gf : 100-pin plastic lqfp (14 x 20)
21 data sheet m16024ej5v0ds pd44321182, 44321362 revision history edition/ page type of location description date this previous revision (previous edition this edition) edition edition 5th edition/ throughout throughout modification ? preliminary data sheet data sheet apr. 2005 deletion ? -a60, -a50y, -a60y p.12 p.12 modification recommended dc v ih (min.) : 1.7 v 2.0 v operating conditions (1/2)
22 data sheet m16024ej5v0ds pd44321182, 44321362 [memo]
23 data sheet m16024ej5v0ds pd44321182, 44321362 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6
pd44321182, 44321362 zerosb is a trademark of nec electronics corporation. the information in this document is current as of april, 2005. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorpor ate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). ? ? ? ? ? ?

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